Serial backplanes have become popular for providing high-speed connections between printed circuit boards (PCBs). Typically, serial backplanes employ a serializer at a transmitting end to convert and transmit data in serial order, and a deserializer at a receiving end to convert the data back to parallel form once received. Such serializer/deserializer (“serdes”) modules have become the benchmark for asynchronous communication and have provided clear advantages over parallel busses.
FIG. 1 is a diagram of two PCBs 110 and 112 connected together via a high-speed serial backplane 114. Printed circuit board 110 includes a central processing unit (CPU) 120 connected to a random access memory (RAM) 122 and logic 124. PCB board 110 also includes a serdes 126 connected to logic 124. The CPU 120, RAM 122, logic 124, and serdes 126 may be part of a programmable logic device (PLD), for example, a field programmable gate array (FPGA) such as Virtex II Pro™ from Xilinx Corp. of San Jose, Calif., which is attached to board 110. Printed circuit board 112 includes circuitry similar to board 110 (and also may be part of a second FPGA), such as serdes 140 connected to logic 142, which in turn is connected to CPU 144 and RAM 146. Serdes 126 is connected to serdes 140 via high-speed serial backplane 114. Serdes 126 transmits serial data over signal line 132 to the receiver at serdes 140. Serdes 140 transmits serial data over signal line 136 to the receiver at serdes 126. Connection points 130, 133, 134, and 137 indicate were a connector may be used to connect the PCBs e.g., boards 110 and 112, to backplane 114.
The PCBs (normally called daughtercards), e.g., PCBs 110 and 112, are affixed to circuit board connectors, which allow the PCBs to be electrically connected to the backplane 114. Typically a series of circuit board connectors are spaced regularly along the length of the backplane. Multiple circuit layers of the backplane route the transmit and receive signals and power to the connectors and hence connect the PCBs to each other. Plated through holes electrically interconnect runs of different circuit layers as needed.
FIG. 2 is a simplified side view of an example of a daughter card connector 210 and its associated backplane connector 220 of the prior art. This simplified view represents the GbX™ 4-Pair daughtercard signal module, i.e., a daughtercard connector, and backplane signal module, i.e., a backplane connector, of Teradyne Inc. of Boston, MA. A daughtercard 212 may be, for example, board 110 or board 112 of FIG. 1. The daughtercard 212 is affixed to daughtercard connector 210. Daughtercard connector 210 is plugged into backplane connector 220. Backplane connector 220 has the pins, e.g., pins 230, 231, 232, 233, 234, 235, 236, and 237. Daughtercard connector 210 has an area 214, which has the corresponding female structures to receive the pins.
Backplane connector 220 is affixed to backplane 222 (which is similar to backplane 114 of FIG. 1). Backplane connector 220 includes an array of pins (e.g., 8×25). FIG. 2 shows a sideview subset of eight pins, e.g., 230–237, and three ground shields 240, 242 and 244 interposed between each pair of pins, e.g., pin pairs 230/231, 232/233, 234/235, and 236/237, respectively. The pin pairs, e.g., 230 and 231, may receive/transmit a differential signal, where, for example, pin 230 may be the positive(P) part and pin 231 may be the negative(N) part of the differential signal. For purposes of illustration, the pins 230–237 are part of a “column”, e.g., column 310, in a connector pin assignment array as shown in FIG. 3. Each ground shield, e.g., 240, 242 or 244, is made up of a metal plate and is connected to ground to provide shielding between the pin pairs.
FIG. 3 shows a prior art connector pin assignment 300 for multiple serdes modules on a daughter card. The connector positions TXP 320 and TXN 322 indicate that the positive transmit signal (TXP) of a first serdes and the negative transmit signal (TXN) of the first serdes is assigned to pins 230 and 231 in a first column 310 and first row 350. The connector positions RXP 324 and RXN 326 indicate that the positive receive signal (RXP) of the first serdes and the negative receive signal (RXN) of the first serdes is assigned to pins in row 350 and column 312 (not shown in FIG. 1). Similarly, the connector positions TXP 330 and TXN 332 indicate that the positive transmit signal (TXP) of a second serdes and the negative transmit signal (TXN) of the second serdes is assigned to row 350 and column 314 (not shown in FIG. 1). The connector positions RXP 334 and RXN 336 indicate that the positive receive signal (RXP) of the second serdes and the negative receive signal (RXN) of the second serdes is assigned to row 350 and column 316 (not shown in FIG. 1). In addition, the connector positions TXP 340 and TXN 342 indicate that the positive transmit signal (TXP) of a third serdes and the negative transmit signal (TXN) of the third serdes is assigned to pins 232 and 233 in column 310 and row 352. The connector positions RXP 344 and RXN 346 indicate that the positive receive signal (RXP) of the third serdes and the negative receive signal (RXN) of the third serdes is assigned to other pins in a second row 352 and column 312 (not shown in FIG. 1). Connector positions TXP 360 and TXN 362 are assigned to pin positions of 234 and 235 in FIG. 1. Connector positions TXP 364 and TXN 366 are assigned to pin positions of 236 and 237 in FIG. 1.
The connector pin assignment 300 of FIG. 3 forms an array with columns 310, 312, 314 and 316, and rows 350, 352, 354, and 356. In each element of the array, for example, column 310 and row 350, is a differential pair, e.g., TXP 320 and TXN 322, indicating a positive and negative portion of a differential signal. Ground shields, e.g. 240, 242, and 244, are interposed between each row, e.g., 350/352, 352/354, and 354/356, respectively. The side view in FIG. 2 of backplane 220 shows only the first column 310 and for the example of the GbX™ connector, there may be 25 columns of which only four columns are shown in FIG. 3.
As the speed of data transmission increases into the gigahertz range and beyond, near-end cross talk becomes a significant problem for connector pin assignments such as that of FIG. 3. As the transmit signal, is relatively much larger than the receive signal, the transmit signal couples with the receive signal. For example, the differential transmit signal from TXP 320 and TXN 322 couples into the signal received by RXP 324 and RXN 326 and also the signal received by RXP 334 and RXN 336. Since linear equalization circuits cannot typically distinguish a signal from the crosstalk, it is difficult to correct for the crosstalk using circuitry alone. In addition, the transmit circuits may have a transmit pre-emphasis which aggravates the crosstalk.
One prior technique used to reduce cross talk was to either completely shield the transmitters or the receivers. For example, in FIG. 3, TXP 320 and TXN 322 would have a ground shields on all four sides. Or, for example, RXP 334 and RXN 336 would have ground shields on all four sides. In effect there would not only be ground shields 240, 242, and 244 in the horizontal direction, but ground shields in the vertical direction (not shown) between columns 310/312, 312/314, 314/316, and so forth. In the case of the GbX™ 4-Pair backplane signal module, there may be 25 columns. This is a difficult and expensive solution and is typically impractical to implement.
Therefore, an improved connector pin assignment is needed to reduce the crosstalk in a high-speed serial backplane, where the ground shields are substantially in only one direction.